1. Field of the Invention
The present invention relates to methods for producing metallic bit lines for memory cell arrays, methods for producing memory cell arrays including such metallic bit lines, and memory cell arrays produced by means of these methods. In particular, the present invention relates to methods and devices which are suitable to be used for planar EEPROMS for so-called xe2x80x9cstand-alonexe2x80x9d applications and for so-called xe2x80x9cembeddedxe2x80x9d applications. The present invention is especially suitable for building up memory cells which are constructed according to the SONOS principle (SONOS=silicon-oxide-nitride-oxide-silicon). Such memory cells can advantageously be used e.g. in a virtual-ground-NOR architecture.
One of the most important development aims in the field of memory cells is the realization of increasingly smaller memory cells, i.e. the use of increasingly smaller chip areas per bit stored. Up to now, it has been considered advantageous to realize compact cells by means of buried, i.e. diffused bit lines. However, bit lines implemented as diffusion areas become increasingly high ohmic as their structural size decreases, since the diffusion depth must be scaled as well, so as to counteract the risk of a punch through between neighbouring bit lines. The problem arising in this connection is that high-ohmic bit lines permit only comparatively small cell blocks so that the utilization degree decreases and the advantage of the smaller memory cells, for which a higher process expenditure must be tolerated, diminishes.
2. Description of the Prior Art
One example of known memory cells with buried bit lines and a virtual-ground-NOR architecture is described in the article: xe2x80x9cNROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cellxe2x80x9d, Boaz Eitan et al, IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545.
It is the object of the present invention to provide methods and devices which permit the realization of very compact memory cells also in larger cell blocks.
According to a first aspect of the present invention, this object is achieved by a method for producing bit lines for a memory cell array, said method comprising the following steps:
providing a layer structure which comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of said substrate, and a gate region layer provided on said sequence of storage medium layers;
producing bit line recesses in said gate region layer, said bit line recesses extending down to the storage medium layer;
producing insulating spacer layers on lateral surfaces of said bit line recesses;
removing the sequence of storage medium layers fully or partly in the area of the bit line recesses;
executing a source/drain implantation in the area of said bit line recesses;
removing the sequence of storage medium layers completely in the area of the bit line recesses, if said sequence of storage medium layers was not completely removed previously; and
producing metallizations on the areas subjected to the source/drain implantation, so as to produce the metallic bit lines, said metallizations being insulated from the gate region layer by the insulating spacer layers.
According to a second aspect of the present invention, this object is achieved by a method for producing a memory cell array, said method comprising the following steps:
providing a layer structure which comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of said substrate, and a gate region layer provided on said sequence of storage medium layers;
producing bit line recesses in said gate region layer, said bit line recesses extending down to the storage medium layer;
producing insulating spacer layers on lateral surfaces of said bit line recesses;
removing the sequence of storage medium layers fully or partly in the area of the bit line recesses;
executing a source/drain implantation in the area of said bit line recesses;
removing the sequence of storage medium layers completely in the area of the bit line recesses, if said sequence of storage medium layers was not completely removed previously;
producing metallizations on the areas subjected to the source/drain implantation, so as to produce the metallic bit lines, said metallizations being insulated from the gate region layer by the insulating spacer layers;
filling the bit line recesses remaining after the production of the metallic bit lines with an insulating material; and
producing word lines which extend substantially at right angles to said bit lines and which are each connected to a plurality of gate regions, said gate regions being produced when the word lines are being produced, by means of suitable patterning of the remaining parts of the gate region layer.
In accordance with preferred embodiments of the present invention, the metallic bit lines are produced by executing a Ti- or Co-silicide process on the exposed substrate areas which were previously subjected to a source/drain implantation, which can also be referred to as bit-line implantation. During the silicide process for producing the metallizations on the source/drain implantations, the future gate structures are preferably provided with a hard mask consisting preferably of nitride. The areas subjected to the source/drain implantation serve as source/drain regions of the storage transistors, the silicidation of these areas serving as a metallic bit line. The gate regions or gate structures, which are initially implemented as strips extending along the bit line in the case of the method according to the present invention, are etched, preferably by a dry-etching process, during the production of the word lines in a self-aligning manner relative to these word lines.
Making use of the method according to the present invention, peripheral transistors can additionally be produced in areas outside of the memory cell array, parallel to the production of the memory cell array. The methods according to the present invention can be used for realizing peripheral transistors with so-called single-workfunction gates, in which all the polycrystalline gate regions are of the same doping type, as well as peripheral transistors with so-called dual-workfunction gates, in which the doping type of the polycrystalline gate regions is adapted to the channel type, i.e. the doping type of the source/drain regions.
According to a third aspect of the present invention, the above object is achieved by a memory cell array comprising:
a plurality of memory cells arranged in a two-dimensional array and realized by field-effect transistors formed in a substrate;
word lines which are arranged in a first direction with respect to the memory cell array and which are connected to gate regions of the memory cells in an electrically conductive manner; and
bit lines extending between the memory cells in a second direction substantially at right angles to said first direction,
the bit lines being defined by metallic structures which are produced directly on the source/drain regions of the memory cells, and insulating means being provided between the metallic structures of the bit lines and the gate regions of the memory cells.
It follows that the present invention provides methods for producing memory cell arrays with metallic bit lines which are self-aligned relative to gate structures, and memory cell arrays including such bit lines. Furthermore, gate structures which are self-aligned relative to metallic word lines are produced according to the present invention. The present invention additionally permits an advantageous incorporation of a parallel production of the memory cell array and of the peripheral circuit structures in the manufacturing process in question.
Due to the production of metallic i.e. metallized bit lines and, in addition, due to the production of metallic i.e. metallized word lines, the present invention permits the formation of large cell blocks having a minimum periphery and, consequently, a high cell efficiency. Due to the use of metallic bit lines, the bit lines can be so narrow that a cell area of 4F2 can be realized, F indicating the possible line width, when the technique used is a lithographic technique; today""s lithographic technologies achieve line widths of 140 nm. In the production method and the structural design according to the present invention, the bit-line plane and the word-line plane can be used as a metallic wiring plane. Furthermore, the method according to the present invention can be combined with the single-workfunction technology as well as with the dual-workfunction technology.